Semiconductor device fabrication is a complex process that involves many manufacturing and testing steps. In some processes, multiple semiconductor devices are being assembled in a common package. For example, multiple integrated circuit (IC) dies can be mounted to an interposer, and the resulting stacked assembly packaged as a single device. The IC dies can be heterogeneous. For example, a package can include a programmable IC die, such as a field programmable gate array (FPGA), and a companion IC die, such as a memory. Currently, the companion IC dies are assembled on the interposer wafer along with the programmable IC dies at the start of the assembly process. Such an assembly flow creates thermal and charge damage to the companion IC dies, as the companion IC dies will go through multiple thermal cycles during the assembly process. Moreover, if the programmable IC die fails electrical testing, the companion IC die will be wasted or otherwise requires removal from the interposer wafer. Thus, the current assembly flow increases costs.